1. Field of the Invention
The present invention relates to the field of computer systems. Specifically, the present invention relates to memory controllers for computers.
2. Related Art
An important component of any computer system is a memory array. The memory array is used for the storage of data and processing instructions for the processor or other resources of a computer system. Computer systems operating in different applications have different requirements as to the size of the memory array. A general purpose computer system typically supports a number of memory configurations in order to optimize the system for a particular application. Different memory configurations are implemented by inserting variable type and size memory devices in the memory array. In most prior art computer systems, the memory array is comprised of dynamic random access memory (DRAM) devices. DRAMs are manufactured as semiconductor devices or chips of various types and sizes. For example, DRAMs of a 64K, 256K, 1M, or 4M bit type are commonly available devices. Further, these devices may include one or more bits of information storage for each location. Thus, a particular memory array may be configured by inserting the appropriate type and size DRAMs as needed for a particular application.
Prior art computer systems also typically include a memory controller for controlling access to the memory array. Although various types and sizes of DRAMs may be installed in the memory array, the memory controller must be configured properly in order to correctly control access to the DRAMs installed in the memory array. In some prior art computer systems, the memory controller is configured by use of hardware switches for specifying a plurality of memory configuration parameters. These parameters include the presence of a memory device in a particular memory bank, the type and/or size of a memory device in a particular bank, and the base or starting address of a particular memory bank. Other memory configuration parameters may be necessary in other computer systems. Computer systems employing hardware switches for configuring the memory controller are prone to problems with improperly configured switches and not conveniently reconfigurable. In fact, any system that requires the pre-computation and storage of base addresses is inherently vulnerable to error conditions where the pre-computed base address does not match the actual memory configuration.
U.S. Pat. No. 4,899,272, titled "Addressing Multiple Types Of Memory Devices", naming inventors Michael G. Fung and Justin Wang, and filed Oct. 23, 1987 (denoted herein as the '272 Patent) discloses a memory addressing system that can accommodate multiple size DRAMs. The '272 Patent teaches a memory addressing system providing a hardware register associated with each pair of banks of DRAMs. These hardware registers are programmable to indicate the type of DRAMs that have been inserted in the particular memory banks and to indicate the starting address of the particular set of memory banks.
Although the '272 Patent describes a more easily configured system than prior art systems using hardware jumpers or switches, the '272 Patent approach nevertheless is subject to significant problems. The approach in the '272 Patent requires that the starting address of each memory bank be determined in advance and programmed into its associated hardware register. The starting address for each memory bank, however, is difficult to compute and awkward to manipulate. Thus, errors caused by an improperly configured hardware register are possible.
Thus, a better memory configuration system for use with variable type and size memory devices is needed.